1. Field of the Invention
The invention relates to a field of digital adders and more specifically to a carry lookahead scheme in an adder.
2. Prior Art
The center of any computer or microprocessor is the arithmetic-logic unit (ALU). One primary function of any ALU is the capability of adding digital numbers. An adder circuit in the ALU provides the means of combining two numbers and generating a sum.
A typical half-adder adds two digits and provides a sum as well as a carry. A full-adder accepts an incoming carry and adds the carry-in as well, wherein a sum and a carry-out are generated. The carry-out functions as a carry-in to the next significant bit. Sequential coupling of individual full-adders provide a complete adder and the extent of the adder is determined by the number of cascaded stages. However, in a simple ripple adder, the processing time is slowed by the need to generate a carry in the preceding stage prior to performing the addition in the current stage.
To overcome this handicap, lookahead circuits were developed. A typical lookahead circuit will look at certain number of bits to be added and generate a carry-out prior to the addition of those bits to derive a sum. Hence, a typical prior art circuit combines a pair of four bits into a stage and provides a carry-out to the next stage prior to the generation of a sum in the stage. The lookahead circuitry reduces the need for rippling through every bit position and thereby reduces processing time. Unfortunately, lookahead circuits become sizeable as the number of bits in a stage is increased. Therefore, the prior art practice was to limit the number of bits to four per stage.
The present invention describes an improved scheme of combining irregular groupings of carry lookaheads to optimize the propagation of a carry. By grouping more bits in the center and less bits in the extremeties, faster carry propagation is achieved. Where higher bit processors are used, such as the 32-bit processors of today, carry propagation delay in the ALU presents a limiting factor to processing speed. The intent of the present invention is to reduce the carry propagation delay.